1. Technical Field
The present invention relates to a loop bandwidth correcting technology, and in particular, to a phase lock loop (PLL) device with correcting function of loop bandwidth and method thereof.
2. Related Art
A PLL is a typical technology for synthesizing a frequency signal, and is often used to design various frequency control loops for frequency tuning of radio waves or clock control of digital products.
Generally, in a PLL, input and output periodic signals have a specific phase relationship. A circuit structure of the PLL mainly includes a phase frequency detector (PFD), a charge pump, a loop filter, a voltage controlled oscillator (VCO), and a feedback unit.
A PLL generally operates as follows: an initial stage is a frequency acquisition stage, and in the frequency acquisition stage, an internal frequency catches up with 90% of a target frequency; after a difference between the internal frequency and the target frequency is within 10%, the PLL enters a frequency locking stage; in the frequency locking stage, a phase is acquired, and finally locking between the phase and the frequency is achieved. Different locked frequencies have different control voltages, reflecting different control parameters for the PLL, thus affecting stability.
Loop bandwidth of a PLL may affect a transient response, integrated phase noise (IPN), relative phase noise (RPN), inter-carrier interference (ICI), and other performance parameters of the PLL. To achieve optimal performance of the PLL, it is crucial to control the loop bandwidth of the PLL well. However, preset loop bandwidth usually changes under the effect of factors such as a change of a semiconductor process, a change of an external component, a change of a power supply, and environmental conditions, leading to a drift of the loop bandwidth.
Nowadays, many correcting technologies for loop bandwidth have been developed, however, they fails to respond to each loop operation result and limits architecture of the PLL, etc.